Many attempts have been made in the prior art to protect semiconductor devices, including bipolar transistors, field effect devices, and integrated circuits against damage due to voltage and current transients. Such protection devices have commonly taken the form of diode or transistor circuits that have been incorporated on the integrated circuit chip for internal transient protection. The design engineer is nevertheless faced with the problem of having to use valuable chip space for forming protection devices. Particularly on devices containing a large number of pins, it has been found that the protection devices occupy a significant amount of space and, therefore, the chip can become undesirably large.
Protection circuits advantageously utilizing silicon controlled rectifier (SCR) arrangements are known, for example, from Avery, U.S. Pat. No. 4,484,561; Kokado et al., U.S. Pat. No. 4,631,657; and Avery, U.S. Pat. No. 4,633,283; and Avery U.S. patent application Ser. No. 07/700,314.
In typical SCR arrangements utilized in the protection of integrated circuits, the trigger or firing voltage under quasistatic conditions is on the order of 25 volts to 40 volts. However, in practice, pulse conditions typically prevail and the actual trigger voltage is generally higher because of the time taken to establish the plasma. When such an SCR arrangement is utilized as part of an ESD protection circuit on a VLSI chip, for example, damage to other parts of the chip could occur before the "snap-back" SCR conduction regime has been established, i.e. before the SCR has achieved its "shorted" state. It is therefore desirable to achieve a lower trigger voltage for the SCR. In U.S. patent application Ser. No. 07/700314 Avery disclosed methods for reducing the trigger voltage of the SCR. As device geometries have shrunk to submicron dimensions the need for even lower trigger voltage protection devices which can be fabricated with a predictable trigger voltage to protect the thin gate oxide have become necessary.